Design and Simulation of Power Efficient 32-bit Vedic Multiplier Using Brent-Kung Adder with Flip-Flop Based Clock Gating

–This paper presents the design and simulation of a power-efficient 32-bit Vedic multiplier architecture integrated with a Brent-Kung adder and flip-flop-based clock gating. The proposed design leverages the Urdhva Tiryakbhyam sutra for multiplication and employs Brent-Kung adders for fast carry propagation. The Brent-Kung adder provides fast parallel-prefix addition with logarithmic delay, improving computation speed compared to traditional adders such as Ripple Carry, Carry Look-Ahead, or Carry Save. Flip-flop based clock gating reduces dynamic power consumption by disabling inactive clock cycles. Simulation results in Verilog HDL demonstrate significant improvements in power efficiency and speed compared to conventional multiplier-adder architectures.