Design and Simulation of Single Master Single Slave Serial Peripheral Interface (SPI) with Adaptive Baud Rate Using Verilog

This paper presents the design and simulation of the Serial Peripheral Interface (SPI) communication protocol using Verilog Hardware Description Language (HDL). The implementation focuses on establishing reliable communication between a master and a single slave device. The design is simulated using Vivado software targeting an Artix-7 FPGA platform. The SPI protocol is widely used in embedded systems due to its simplicity, high speed, and full-duplex communication capability. In this work, key SPI signals such as Serial Clock (SCLK), Master Out Slave In (MOSI), Master In Slave Out (MISO), and Chip Select (CS) are implemented and analysed. The results demonstrate successful data transmission between master and slave through simulation waveforms. The proposed design ensures efficient synchronization between master and slave devices with minimal latency. The simulation results validate the reliability and robustness of the SPI protocol for high-speed embedded system applications.