Design and Verification of an Efficient Packet Based Switching Network-on-Chip

With large number of cores and increased delay in SoCs, traditional point to point or bus based communication architecture becomes a new bottleneck. Traditional communication architectures cannot meet system requirements of bandwidth, latency, and power consumption.Integrated switching network has been proposed as an alternative approach to interconnect cores in SoC. Such network rely on a scalable and reused communication platform, called network on chip ( NoC ) system,to meet two major requirements: reusability and scalable bandwidth. The NOC architecture is a m × n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical-architectural level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (IP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the on-chip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multi-processor.