Design of a High-Speed, Low-Power Dadda Multiplier Based on XOR–XNOR Hybrid Full Adder and NMOS Power Gating

In this paper, Digital multipliers are very important for the performance of VLSI systems. However, traditional designs like array multipliers suffer from high delay due to carry propagation and also consume more power. To overcome these problems, this paper presents the design of an optimized 8-bit Dadda multiplier that improves both speed and power efficiency.In this design, the conventional CMOS full adders are replaced with hybrid logic full adders based on XOR-XNOR cells. This change helps to reduce logic levels, internal capacitance, and switching activity, which directly improves the speed of operation. As a result, the generation of sum and carry becomes faster.To further reduce power consumption, an NMOS power gating technique is used. A sleep transistor is placed between the logic circuit and ground to reduce leakage current when the circuit is idle. This helps in minimizing static power dissipation.The proposed design is implemented and simulated using Cadence tools. The results are compared with a conventional Dadda multiplier, and significant improvements are observed. The propagation delay is reduced by 55.7%, from 740.0 ps to 327.3 ps, showing a clear increase in speed. Similarly, the total power consumption is reduced from 1.03 mW to 998.7 µW, improving overall efficiency.Although there is a small increase in area, with the transistor count increasing from 1744 MOS to 1752 MOS, the performance improvements in speed and power make it acceptable. Finally, the proposed multiplier offers a good balance between high speed, low power, and area, making it suitable for applications such as digital signal processing, image processing, and battery-operated embedded VLSI systems.