Design of Glitch-Reduced Kogge–Stone Adder Using Balanced Delay and Transistor Optimization

In this project, a glitch-reduced Kogge-Stone Adder was successfully designed and analyzed. The main issue with the conventional design was excessive power consumption due to glitches caused by unequal delays. To address this, delay balancing and buffer insertion techniques were applied. Additionally, transistor sizing was optimized to improve overall efficiency. The simulation results confirm that the proposed design reduces switching activity and improves power performance. Although there is a slight increase in delay, the overall improvement makes it suitable for modern low-power applications.

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