Design of Low Power Advanced Encryption Standard Using Verilog HDL

The Advanced Encryption Standard (AES) is a widely used symmetric key encryption algorithm that secures digital data in modern communication systems. Conventional AES hardware implementations often consume high power, limiting their efficiency in resource-constrained environments. This paper presents a low-power AES hardware design implemented in Verilog HDL. The base design uses AES-128 with a 128-bit data block and 128-bit key, while the proposed design enhances security with a 256-bit key. Flip-flop based clock gating is applied to reduce dynamic power by minimizing unnecessary switching activity. Simulation results demonstrate that the proposed architecture effectively reduces power consumption while maintaining encryption performance, making it suitable for applications in IoT devices, embedded systems, and other low-power environments.