Design of Low POWER CLA using Coding-Based Partial MRF Method

One of the biggest challenges in designing circuits with low power consumption is reliability. It is common practice to employ Markov Random Field (MRF) approaches to deal with random noise in circuits operating at very low voltages. For smaller, simpler circuits, these function well, but for larger, more intricate designs, they become challenging. This work presents a novel method known as coding-based partial MRF (CPMRF). The CPMRF pair, which utilizes a shared MRF network to conserve space, is a unit that combines several logic processes. Additionally, by employing a coding technique that reinforces “1s” and “0s,” it increases resistance to noise. The design is therefore more economical and efficient than previous approaches. The Cadence tool is used in this project to develop a Carry-look ahead adder (CLA) using CPMRF pairs. Measurement results show that, in comparison to the master-and-slave MRF CLA design, the CPMRF CLA can achieve high noise tolerance with a 20% improvement while taking up 37.7% less space and using 93% less power.