Design of Mixed Radix FFT Algorithm Using FPGA

FFT algorithms like radix-2 are efficient for signal lengths that are powers of two, many practical applications require FFT computation for arbitrary input sizes. To address this limitation, this project presents the design and FPGA-based implementation of a Mixed Radix FFT algorithm, which accommodates composite input sizes by combining multiple radix strategies (e.g., radix-2, radix-3, radix-5). The proposed architecture leverages the parallel processing capabilities of Field Programmable Gate Arrays (FPGAs) to optimize performance, reduce latency, and improve resource utilization. The design is implemented using hardware description languages (HDLs) such as VHDL or Verilog, synthesized and verified on a suitable FPGA development board. Key aspects of the design include modular decomposition, pipelining, and memory-efficient data management. he results demonstrate that the Mixed Radix FFT design on FPGA offers high flexibility and computational efficiency, making it well-suited for real-time signal processing applications in embedded systems.