DESIGN OF PIPELINING AND PARALLEL PROCESSING ARCHITECTURE OF DIGITAL FILTERS

DESIGN OF PIPELINING AND PARALLEL PROCESSING ARCHITECTURE OF DIGITAL FILTERS

S.Hari Krishnan1,D.Nagaraju2,B.Venkatesu3, S.Sadiq Vali4

1Assosciate  Professor, Dept. of  ECE, Sanskrithi School of Engineering, Puttaparthy, India

2Assosciate  Professor, Dept. of  ECE,Sanskrithi School of Engineering, Puttaparthy,India

3Assistant Professor, Dept. of  ECE, Sanskrithi School of Engineering, Puttaparthy, India

4Assistant Professor, Dept. of  ECE, Sanskrithi School of Engineering, Puttaparthy, India

ABSTRACT

The implementation of Finite impulse response (FIR) filters and Infinite impulse response (IIR) filters with enhanced speed has become more demanding in VLSI technology. Using VHDL (Very High Speed Integrated Circuit Hardware Descriptive Language)  designing and implementing a  pipelining and parallel processing architecture for FIR and IIR filter to reduce the power consumption and delay of the filter. The proposed architecture is compared with the original FIR and IIR filter respectively in terms of speed, area, and power. Also, the proposed architecture is compared with existing architectures in terms of delay. The implementation is done by using VHDL codes. FIR and IIR filters structures are implemented at 1200 KHz clock frequency. Synthesis and simulation have been accomplished on Artix-7 series FPGA, target device (xc7a200tfbg676) (speed grade -1) using VIVADO 2016.3.

KEYWORDS

DSP, FIR, FPGA, IIR, MIMO.