Design of Ultra-Low Power Consumption Approximate 4–2 Compressors based on the Compensation Characteristic

Applications in digital signal processing that are inherently tolerant of inaccurate computing results are the ones that first use approximate computing. These circuits’ electrical performance is enhanced by utilising the approximate arithmetic blocks. Some of the most basic building elements of computer mathematics are multipliers. In addition, the parallel multipliers frequently use the 4-2 compressors to speed up the partial product compression process. Three novel approximate 4-2 compressors used in 8-bit multipliers are shown in this letter. The approximation multiplier’s error performance is enhanced when an error-correcting module (ECM) is paired with the recommended 4-2 compressors. An improved level of energy efficiency is brought about by this short by halving the number of outputs from the projected 4-2 compressor. Simulated findings show that the suggested approximation compressors UCAC1, UCAC2, and UCAC3 reduce latency by 24.76%, 51.43%, and 66.67%, power by 71.76%, 83.06%, and 93.28%, and area by 54.02%, 79.32%, and 93.10%, respectively, as compared to the exact 4-2 compressors. And using these suggested compressors in 8-bit multipliers results in an average power consumption reduction of 49.29%.