Designing Half-Adder with CMOS Technology using Artificial Neural Network with Verilog Implementation

In this study we want to design a Half-Adder with the help of Artificial Neural Network and design will be made by Complementary metal oxide semiconductor(CMOS).When we design any COMS circuit always we keep in mind that should be in minimum at cost .In this study we have used multi layer ANN to design the circuit. In our study neurons are treated like transistors and weights are used to adjust the value; like negative value as an inverter.