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ArticlePeer ReviewedOpen AccessPlagiarism Passed
Paper ID:IJSREM67904

Development of a Reconfigurable Serial Communication Engine Based on UART Protocol

Stream/Area:

-

Subject:

-

Paper ID:

IJSREM67904

Volume:

10 |

10 |

Oct 2026

Pages:

1-6

Publication Frequency:

Monthly (12 issues per year)

DOI
Digital Object Identifier
10.55041/IJSREM67904

License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.

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Authors

MOHAMMAD YUSUB

MOHAMMAD YUSUB

ELECTRONIC AND COMMUNICATION ENGINEERING

CMR TECHNICAL CAMPUS

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PA

P. Aishwarya

ELECTRONIC AND COMMUNICATION ENGINEERING

CMR TECHNICAL CAMPUS

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MP

M. Pallavi

ELECTRONIC AND COMMUNICATION ENGINEERING

CMR TECHNICAL CAMPUS

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CRK

Ch. Ranjith Kumar

ELECTRONIC AND COMMUNICATION ENGINEERING

CMR TECHNICAL CAMPUS

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Mentors

VM

V. Mounika

ELECTRONIC AND COMMUNICATION ENGINEERING

CMR TECHNICAL CAMPUS

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Abstract

Universal Asynchronous Receiver/Transmitter (UART) is widely used for serial data exchange between processors, controllers, and peripheral devices because it uses a simple interface and does not require a shared clock line. Conventional UART implementations often use predefined communication settings, which can limit adaptability when system requirements change. This paper presents the project design of a reconfigurable UART serial communication engine using Verilog Hardware Description Language (HDL). The architecture includes a transmitter, receiver, baud-rate generator, shift registers, and finite-state-machine (FSM) control logic. The intended configuration options include baud rate, data length, parity mode, and stop-bit selection. The supplied project material includes simulation waveform screenshots; exact measured performance values are not readable from the composite screenshot, so no numerical performance claims are made.

KEYWORDS

UART Verilog HDL FPGA serial communication finite-state machine configurable baud rate.

Cite This Article

MOHAMMAD YUSUB, P. Aishwarya, M. Pallavi, Ch. Ranjith Kumar, V. Mounika, "Development of a Reconfigurable Serial Communication Engine Based on UART Protocol," International Journal of Scientific Research in Engineering and Management, vol. 10, no. 10, pp. 1-6, Oct 2026. https://doi.org/10.55041/IJSREM67904

Full Article/Conclusion

This paper describes a reconfigurable UART engine using Verilog HDL, with separate transmit, receive, timing, shift-register, and FSM-control blocks. Configurable communication parameters can make the interface adaptable to different embedded-system requirements. The supplied screenshots show waveform and schematic views, but detailed performance claims require readable waveforms and verified tests.

References

[1] R. Kalyan Kumar et al., “Implementation of UART design using Verilog HDL to avoid data losses in transmission,” 2024 2nd International Conference on Networking and Communications (ICNWC), IEEE, 2024. [2] P. Anuradha et al., “Enhancing high-speed data communications: Optimization of route controlling network on UART implementation,” IEEE Access, vol. 12, pp. 123514–123528, 2024. [3] C. Naidu, “A 16-byte asynchronous receiver and transmitter using Verilog HDL for real time applications,” 2024 2nd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT), IEEE, 2024. [4] J. Cheng et al., “On the maximum UART size achieved in a class of constructions of optical priority transmissions,” Journal of Communications and Networks, vol. 25, no. 4, pp. 429–439, 2023. [5] S. Chaturvedi, M. N. Saranya, and R. Rao, “Design of Asynchronous Receiver for Asynchronous Transmission,” 2022 International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), IEEE, 2022. [6] D. Han and W. Chen, “Implementation of UART Module with Cryptographic Support: A cross-layer approach,” IEEE Wireless Communications Letters, vol. 9, no. 9, pp. 1370–1373, 2020. [7] S. Basu et al., “FPGA Implementation of UART with BIST Technique,” 2019 4th International Conference on Electrical Information and Communication Technology (EICT), IEEE, 2019. [8] K. Tsuru, “A Theoretic Universal approach to in-network management,” IEEE/ACM Transactions on Networking, vol. 26, no. 6, pp. 2443–2456, 2018. [9] Y. Sun et al., “Throughput modeling and analysis of random access in narrowband Internet of Things,” IEEE Internet of Things Journal, vol. 5, no. 3, pp. 1485–1493, 2017. [10] Masato and A. Lawi, “The impact of message transmission scheduling in DTN message delivery across multiple islands,” 2017 IEEE Asia Pacific Conference on Wireless and Mobile (APWiMob), 2017.

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Publication Date

10/14/2026

Peer Review Type

Double-Blind Peer Review

Review Rounds: 2

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