Development of the Calculator Interface in Verilog HDL using a 5-stage Pipelined MIPS32 Processor

Development of the Calculator Interface in Verilog HDL using a 5-stage Pipelined MIPS32 Processor

Shashwat Shukla1, Shoyab Ahmad2, Dr. Indu Prabha Singh3

1shashwat.0410.shukla@gmail.com,2 aahmadshoyab8808@gmail.com, indu.ec@srmcem.ac.in3

1,2Department of Electronics and Communication Engineering, Shri Ramswaroop Memorial College of Engineering and Management, Lucknow, India

Abdul Kalam Technical University(AKTU), Lucknow, India

Abstract – This work aims to develop a calculator capable of performing fundamental mathematical operations such as addition, subtraction, multiplication, division, factorial, square root, square, and cube. To achieve this, it employed the MIPS32 processor, which adopts a five-stage pipelined architecture and comes with 32 registers. To design the calculator interface, we utilized Verilog HDL programming language and the ModelSim software. This paper presents an extension to the calculator interface design in Verilog HDL using a MIPS32 microprocessor. The original design was developed as a simple calculator interface, allowing users to perform basic arithmetic and logic operations.

An interface module is developed where the processor module is instantiated to offer the two-phase clock input and control signals to the processor and for the user inputs. After selecting the operation and providing the operands, the corresponding operation is performed, and the output is displayed. The extension presented in this paper focuses on improving the user experience and expanding the functionality of the calculator interface.

Index Terms –    MIPS32,   Interface,   Verilog,    ModelSim, Calculator