Distributed Arithmetic for FIR Filter Implementation on FPGA

Distributed Arithmetic for FIR Filter Implementation on FPGA

Sonu Malviya1 & Prof. Aashish Patidar2

1PG Scholar, Department of Electronics & Communication Engineering

2Assistant Professor, Department of Electronics & Communication Engineering

1, 2 PCST Indore

ABSTRACT: This Project describes the implementation of FIR filters on FPGA based on traditional method costs considerable hardware resources, which goes against the decrease of circuit scale and the increase of system speed. It is very well known that the FIR filter consists of Delay elements, Multipliers and Adders. Because of usage of Multipliers in our design gives rise to 2 demerits that are (I) Increase in Area and (II) Increase in the Delay which ultimately results in low performance (Less speed). A new design and implementation of FIR filters using Distributed Arithmetic is provided in this project to solve this problem. Distributed Arithmetic structure is used to increase the resource usage while pipeline structure is also used to increase the system speed. In addition, the divided LUT method is also used to decrease the required memory units. The simulation results indicate that FIR filters using Distributed Arithmetic can work stable with high speed and can save almost 50 percent hardware recourses to decrease the circuit scale, and can be applied to a variety of areas for its great flexibility and high reliability.

Keywords: FIR Filter, FPGA, Look-Up Table, Multipliers and Adders, Distributed Arithmetic.