Efficient Data Transfer in VLSI Systems using Smart Buffering and Routing Techniques

The increasing use of Network-on-Chip (NoC) interconnect schemes is driven by their versatility and ability to scale efficiently. In NoCs, routers are critical components that significantly influence both performance and cost. To overcome design challenges and improve NoC router efficiency, a variety of new techniques have been integrated. We present a novel NoC router design with multiple local ports, created using Verilog models. The main objectives of this design are to minimize the router’s physical size and enhance the speed of data transmission. The architecture leverages XY routing and incorporates optimized buffering, Credit-Based Flow Control, and a Deterministic Clock Approach. The proposed design is evaluated in terms of area usage and operating frequencies. Using distributed control mechanisms, the routers achieve autonomous operation without the need for complex handshaking processes, resulting in improved efficiency and scalability. This Multi-Local Router design is capable of handling multiple independent data requests concurrently, making it ideal for managing high data traffic in advanced Field Programmable System-on-Chips (FPSoCs). The design’s strengths in Power, Performance, and Area (PPA) optimization make it particularly suited for computationally demanding applications. To validate its effectiveness, the router was implemented and synthesized on a Xilinx Virtex 4 FPGA (4vsx25ff668-12), demonstrating its practical viability. This breakthrough paves the way for more efficient NoC implementations in future FPSoC designs.