Energy-Efficient and High-Speed Design of CMOS D Flip-Flops and Counters Using Double-Gate FinFET Technology

Energy-Efficient and High-Speed Design of CMOS D Flip-Flops and Counters Using Double-Gate FinFET Technology

Alakunta Umadevi1 , CH. Ramamohan2
1PG Scholar, Dept. of ECE, SVIT, Ananthapuramu

2 Research Supervisor, Associate Professor, Dept. of ECE, SVIT, Ananthapuramu

ABSTRACT:

As semiconductor technology progresses, the need for energy-efficient digital circuits continues to rise, especially in applications such as portable devices and data centers. FinFET (Fin Field Effect Transistor) technology has emerged as a revolutionary advancement, offering enhanced control over short-channel effects, thereby minimizing power leakage and improving overall efficiency. This paper explores the design and simulation of counters utilizing FinFET-based D Flip-Flops at the 10nm technology node, implemented in LT-Spice, a popular circuit simulation tool. Compared to conventional CMOS designs, FinFET-based counters exhibit a remarkable reduction in power consumption and noise, with improvements of 57.13% and 46.02%, respectively. Additionally, asynchronous and Johnson counters implemented with FinFET technology outperform their CMOS counterparts in terms of speed and reliability. These findings affirm that FinFET technology is a viable solution for achieving high-speed, low-power digital circuits, making it an ideal choice for future semiconductor designs.
Keywords: FinFET Technology, CMOS Limitations, Short-Channel Effects, D Flip-Flop Design, LT- Spice Tool, Power Efficiency, Noise Reduction, Semiconductor Advancement.