Fast Binary Counters and Compressors Generated by Sorting Network

Fast Binary Counters and Compressors Generated by Sorting Network

1Pallepati Deepika, 2Marneni Swapna, *3Srinivas Bachu

1,2,3Department of ECE,

1,2,3Siddhartha Institute of Technology & Sciences, Narapally, Ghatkesar, Medchal-Malkajgiri, Telangana, India

bachusrinivas@gmail.com

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Abstract:  A crucial path in different DSP units involves the parallel summing of several operands. Compressors and counters with a high compression ratio are required to accelerate the summation. This article presents the sorting network based exact/approximate (4:2) compressors and quick saturated binary counters. When one-hot code sequences are the only way to encode reordered sequences, sorting networks are employed. There is an uneven distribution of inputs to the counter. By connecting the rearranged sequence to the one-hot code sequence using three distinct Boolean equations, the counter's output Boolean expressions can be considerably reduced. In order to achieve 27.0% improvement in delay, 26.2% improvement in area-delay product, and 52.0% improvement in power-delay product, we use the aforementioned technique to construct and optimise the (7,3) counter. The (15,4) counter is built in a similar fashion; it uses far less power and space while achieving a delay that is around 35.3% shorter. Instead, the performance of the built (31.5) counters increases by about 26.7% as the area increases. Incorporating counters into a 16×16 bit multiplier improves the multiplier's performance in area delay product by 31.8% and power delay product by 32.1% when compared to other designs of counters. The area-delay product is improved by 10.2% to 37.4% and the power-delay product by 22.3% to 48.0% when an 8×8 bit approximate multiplier is used to construct exact/approximate (4:2) compressors.

Index Terms - Binary Counters, Sorting Network, Compressors.