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Stream/Area:
-
Subject:
-
Paper ID:
IJSREM68441
Volume:
10 |
10 |
Oct 2026
Pages:
1-3
Publication Frequency:
Monthly (12 issues per year)
License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.
ELECTRONICS AND COMMUNICATION ENGINEERING
EAST WEST INSTITUTE OF TECHNOLOGY
ELECTRONICS AND COMMUNICATION ENGINEERING
EAST WEST INSTITUTE OF TECHNOLOGY
ELECTRONICS AND COMMUNICATION ENGINEERING
EAST WEST INSTITUTE OF TECHNOLOGY
ELECTRONICS AND COMMUNICATION ENGINEERING
EAST WEST INSTITUTE OF TECHNOLOGY
This paper presents the design of an FPGA-based real-time face-detection system in which a Tang Nano FPGA performs camera acquisition and initial image processing, while a personal computer performs face recognition and database matching. The FPGA pipeline comprises pixel acquisition, RGB processing, RGB-to-YCbCr conversion, skin-region thresholding, binary segmentation, noise filtering, candidate-region analysis, bounding-box generation, and face region-of-interest extraction. Detected face information is transferred to a PC through a suitable USB/UART-class interface. The PC application, implemented using Python and OpenCV, performs preprocessing, feature comparison against registered users, known/unknown classification, confidence display, and event logging. The proposed architecture separates deterministic pixel-level processing from computationally intensive recognition, providing a practical hardware-software co-design platform for real-time computer-vision education and prototyping.
KEYWORDS
This paper described a Tang Nano FPGA-based real-time face-detection system with PC-assisted recognition. The FPGA performs camera acquisition and a hardware pipeline consisting of color conversion, segmentation, filtering, region analysis, bounding-box generation, and ROI selection. The PC performs recognition, user database matching, monitoring, and history logging. The resulting system is a compact hardware-software co-design platform for demonstrating FPGA-based digital image processing and flexible software-based identity recognition.
[1] P. Viola and M. Jones, “Rapid object detection using a boosted cascade of simple features,” in Proc. IEEE Comput. Soc. Conf. Comput. Vis. Pattern Recognit. (CVPR), 2001, pp. I-511–I-518. [2] R. C. Gonzalez and R. E. Woods, Digital Image Processing, 4th ed. Pearson, 2018. [3] G. Bradski, “The OpenCV Library,” Dr. Dobb’s Journal of Software Tools, 2000. [4] S. Hauck and A. DeHon, Eds., Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann, 2008. [5] Gowin Semiconductor, “GOWIN FPGA Design Software and Tang Nano device documentation,” vendor documentation.
Publication Date
10/29/2026
Peer Review Type
Double-Blind Peer Review
Review Rounds: 2
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Conflict of Interest
The authors declare no conflict of interest related to this research work.
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No funding information available for this research.
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