Floating Point Multiplier using High Performance Adders and Multipliers

Floating Point Multiplier using High Performance Adders and Multipliers

Mr.Chethan B R1, T S Samarth2, Praveen T R3 , Vishwas V S4, Mruthyunjaya S D5

1Proffessor, 2Final year Student, 3Final year Student, 4Final year Student, 5Final year Student,

Department of Electronics and Communication Engineering P E S Institute of Technology and Management, Shimoga

Abstract -This paper presents a high-performance floating-point multiplier designed using advanced adder and multiplier architectures to enhance computational efficiency and speed for FPGA-based applications. The design employs Carry Bypass Adder (CBA) and Kogge-Stone Adder (KSA) to optimize partial product accumulation, along with Wallace Tree and Systolic Multiplier architectures for efficient parallel multiplication. Implemented in compliance with the IEEE 754 single-precision floating-point standard, the proposed multiplier is synthesized and simulated using the Vivado design suite. Comprehensive analysis highlights the trade-offs between the architectures in terms of latency, power consumption, and resource utilization. The results demonstrate significant improvements in performance, making this design ideal for high-speed applications such as signal processing and machine learning.

Key Words:  IEEE 754, FPGA, High-Speed Computation, Low Latency, Resource Optimization.