FPGA Implementation and Architecture Design of Polar Encoder For 5g Nr-: N28 Bits

Specifically concerning the N28 code block length (28 bits), the project concentrates on the FPGA realization and architectural design of a polar encoder for 5G NR (New Radio). Polar codes are a type of error- correcting code that have garnered a lot of interest thanks to their capacity-achieving performance under the 5G communication standards. The ambition of the project to design a hardware-efficient FPGA architecture running the polar encoding algorithm and to maximize performances including throughput, power efficiency, and space. Developing a polar code encoder using successive cancellation decoding and hardware optimization techniques to meet the demanding performance and reliability criteria of 5G NR systems is among the key parts of the design. The FPGA solution is expected to deliver real-time encoding capability suitable for modern wireless networks’ fast communication requirement