FPGA IMPLEMENTATION OF 8085 MICROPROCESSOR CONUTOL UNIT

This paper presents an FPGA-based educational model of 8085-style control sequencing using a Verilog finite state machine and the PYNQ-Z2 platform. The design exposes opcode-dependent state progression, a three-bit T-state code, and selected bus-control signals including ALE, RD_n and WR_n. The supplied behavioural-simulation waveform records the clock, reset, opcode and control-signal activity for the displayed testbench sequence. The project provides a practical link between microprocessor timing concepts, RTL design, simulation and FPGA implementation. Further work is required to verify every supported instruction against reference timing and to document measured implementation metrics.

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