FPGA-Oriented Implementation and Simulation Verification of an I-CDPK Codec

This work demonstrates a structured FPGA-oriented simulation workflow for an I-CDPK codec using signed Q7.14 arithmetic and SystemVerilog. Across 5,000 baseline chaotic samples, the 18 transmit/receive records achieved full keying and demodulation agreement in Vivado/XSim without serial mismatches. Future work focuses on FPGA hardware deployment and BER analysis.

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