FPGA Performance Characterization of an 8-Bit Ordinary Truncated Multiplier under Progressive Timing Constraints

This work presents an 8-bit ordinary truncated multiplier has been characterized on a Zynq-7000 XC7Z020 FPGA over 17 post-route timing targets from 50 to 225 MHz. With CUT=6, 21 of the 64 elementary partial products are eliminated and no correction term is introduced. All measured runs maintain positive setup WNS; at the 225-MHz target the routed design reports +0.413 ns WNS, 4.031 ns critical delay, a slack-derived frequency estimate of 248.08 MHz, 72 LUTs, 34 FFs, 23 mW dynamic power, 0.0927 nJ PDP, and 290.23 LUT·ns ADP. Relative to the 50-MHz implementation, timing-driven optimization reduces critical delay by approximately 43.5% while LUT count increases by 33.3%. ADP nevertheless improves by approximately 24.6%. Exhaustive arithmetic evaluation shows all possible input combinations MED=80.25, WCE=321, error rate=93.75%, and mean signed error=-80.25, verifying the expected one-sided bias of uncompensated truncation. This study consequently establishes a controlled FPGA and numerical reference point for the next phase, in which fixed-bias and boundary-weighted compensation methods can be compared according to the additional hardware needed to recover accuracy.

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