FSM-Based Area Efficient AES-128 Encryption Processor with Pipelined Round Architecture for FPGA Security Applications

The Advanced Encryption Standard (AES) is one of the most widely used symmetric key cryptographic algorithms for secure data communication in modern digital systems. With the rapid growth of Internet of Things (IoT), embedded systems, and FPGA-based applications, there is an increasing demand for high-speed and area-efficient hardware encryption architectures. Traditional software-based encryption methods suffer from higher latency and lower performance, while fully pipelined hardware AES architectures consume significant hardware resources. This project presents the design and implementation of an FSM-Based Area-Efficient AES-128 Encryption Processor with a partially pipelined round architecture using Verilog HDL. The proposed design utilizes a finite state machine (FSM) to control the AES encryption process efficiently while reusing a single AES round block across multiple rounds to reduce hardware utilization. In addition, partial pipelining is introduced within the AES round operations to improve timing performance and throughput without significantly increasing the silicon area. The architecture consists of major AES transformation stages including SubBytes, ShiftRows, MixColumns, AddRoundKey, and Key Expansion. A dedicated key expansion module dynamically generates all required round keys for AES-128 encryption. The entire design is verified using standard NIST AES test vectors, and the obtained ciphertext output matches the expected AES encryption results accurately. Simulation and waveform analysis are carried out using Icarus Verilog and GTKWave tools. The experimental results demonstrate that the proposed architecture achieves a balanced trade-off between hardware area and encryption throughput, making it highly suitable for FPGA-based secure communication systems, embedded platforms, and resource-constrained IoT devices. The modular and scalable structure of the design also enables future enhancement toward AES-192, AES-256, and advanced low-power cryptographic architectures.