Full Adder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output

Full Adder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output

Rupam Sardar1, Sudip Ghosh2, Bimal Datta3

1Budge Budge Institute of Technology, Kolkata – 700137,India

2Indian Institute of Engineering Science and Technology, Botanical Garden Area, Howrah, West Bengal 711103

3Budge Budge Institute of Technology, Kolkata – 700137, India

Abstract:

The goal of this research is to create Full-Adder gate using a Complementary Metal Oxide Semiconductor (CMOS) and an Artificial Neural Network.We constantly bear in mind that any COMS circuit we design should be as inexpensive as possible.Multilayer ANN was employed in this work to create the circuit. Weights are employed to modify the value in our study, treating neurons as transistors and treating negative values as inverters.We are also designing Verilog-HdL Code to simply apply the full adder for experimenting an artificial neural network assigning weights to get appropriate results.

Keywords: Full Adder, CMOS,ANN,Verilog-HDL