GDI based Area Delay and Power Efficient Braun Multiplier

GDI based Area Delay and Power Efficient Braun Multiplier

B.Likhitha#1, B.Priyanka#2, D.Bhavani#3, D.Goutham Varma#4, M.Shankar Mouli#5

Bachelor of Technology,Electronics and Communication Engineering, Lendi institute of engineering and technology
Vizianagaram, Andhra Pradesh, India

Abstract — Multipliers are the most commonly used elements in today's digital devices. Multiplications are very expensive and slow the overall operation. As multipliers are complex circuits and must operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. Today the requirements for minimizing the delay, area and power of multiplier circuit improve the efficiency of whole system which drives the technology to the next level. To accomplish the needs of today’s digital devices, various types of low power and high performance multipliers have been designed. To achieve such requirements high performance multipliers are always preferable. The proposed technique provides low power dissipation and less propagation delay. By using this GDI based multiplier the number of transistors required for the circuit is also minimized. So an efficient multiplier design can be achieved through this technique.

Keywords — multiplier, low power, less area, GDI