High-Performance AES Encryption Architecture on FPGA Using Pipelined Simulation and Adaptive NoC Routing

– Optimization of reconfigurable multicore processors through pipelining of cryptographic modules offers significant improvements in both performance and security. This work presents a design and implementation of pipelined AES and SHA modules on an FPGA platform to enhance throughput and reduce power consumption in a multicore processor architecture. Simulation results using ModelSim demonstrate that the pipelined approach increases the number of processed packets per second and decreases latency compared to existing baseline designs. Additionally, power analysis shows reduced energy usage without compromising cryptographic strength. The proposed design achieves a balanced trade-off between speed, security, and resource utilization, making it suitable for secure high-speed applications.