High-Speed Area-Efficient VLSI Architecture of Three Operand Binary Adder

High-Speed Area-Efficient VLSI Architecture of Three Operand Binary Adder

Chilagani Keerthan1, Bathini Trinay2, Mr M Ravinder3

1,2,3,4 UG Scholars, 5Assistant Professor

1,2,3,4,5 Department of ECE[Electronics and Communication Engineering],

1,2,3,4,5 Guru Nanak Institutions Technical Campus, Hyderabad, Telangana, India

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Abstract

This paper proposes a novel high-speed three-operand binary adder architecture, namely the Han-Carlson adder, which mitigates the inherent limitations of traditional Carry Save Adders (CSAs). The CSA's drawbacks, including slow carry propagation and increased power consumption, are alleviated by the Han-Carlson adder's innovative prefix computation and carry lookahead architecture.The Han-Carlson adder's design exploits the benefits of prefix computation to generate the carry signals in parallel, thereby reducing the critical path delay. Furthermore, the carry lookahead mechanism enables the adder to propagate the carry signals rapidly, resulting in improved speed and reduced power consumption.The proposed Han-Carlson adder is specifically designed for high-performance digital systems, where fast and efficient addition of multiple operands is crucial. Simulation results demonstrate the superiority of the Han-Carlson adder over traditional CSAs, showcasing its potential as a high-speed and area-efficient solution for digital arithmetic applications.

Keywords

Han-Carlsonadder,Three-operand binary adder, CarrySave Adder (CSA) ,Prefix computation ,Carry lookahead  architecture