High-Speed Multiply–Accumulate Unit Based on Brent–Kung Adder with Pipelining

The Multiply-Accumulate (MAC) Unit is a crucial component in all DSP Applications, due to its ability to perform high speed arithmetic operations. This Project aims to design and implement an 8-bit MAC Unit capable of performing multiplication and accumulation operations. The MAC Unit employs the same multiplier unit implemented using different adder architectures while keeping the multiplier constant. Conventional MAC units use Ripple Carry Adders (RCA) and Carry Look-Ahead Adders (CLA), which suffer from high carry propagation delay and increased hardware complexity respectively. To overcome these limitations, parallel prefix adders are proposed, such as Kogge–Stone (KSA), Ladner– Fischer (LFA), Brent Kung Adder with Pipelining are integrated into the MAC unit. The structures were formed using Verilog Hardware Description Language (HDL) and implemented on Xilinx ISE, with simulation carried out using Model Sim.