Loading article...
Loading article...
Stream/Area:
-
Subject:
-
Paper ID:
10.55041/IJSREM16424
Volume:
6 |
9 |
Sep 2022
Pages:
Publication Frequency:
Monthly (12 issues per year)
License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.
This study offers revolutionary 24-transistors (24T), 1-bit ‘full-adder’ (FA) for energy-efficient DSP applications. A hybrid XNOR circuit is used to create the proposed 1-bit FA. The hybrid XNOR circuit is built utilising the GDI (gate-diffusion-input) technology, TG (transmission gate), and SCMOS (static CMOS) logic. To evaluate the proposed FA’s performance, ‘Design Metrics’ (DMs) such as power, delay, ‘power-delay-product’ (PDP), and area are compared to state-of-the-art FAs. All of the FAs under examination were built and simulated under common ‘process-voltage-temperature’ (PVT) conditions for a fair comparison
KEYWORDS
Publication Date
9/22/2022
Peer Review Type
Double-Blind Peer Review
Review Rounds: 2
Documents
Article Views
0
Total views since publication
PDF Downloads
1
Total downloads since publication
Geographic Reach
5
Digital Preservation: This article is permanently archived on Zenodo and complies with all data preservation standards across major indexing platforms.
Plagiarism Screening
This manuscript has been checked for plagiarism using TurnitinPlagiarismChecker software.
Conflict of Interest
The authors declare no conflict of interest related to this research work.
Funding Information
No funding information available for this research.
Related research in the same subject area
Loading similar articles...