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Stream/Area:
-
Subject:
-
Paper ID:
IJSREM66987
Volume:
10 |
8 |
Aug 2026
Pages:
1-10
Publication Frequency:
Monthly (12 issues per year)
License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.

Electronics and Communication Engineering
JNTU-GV College of Engineering, Vizianagaram

Electronics and Communication Engineering
JNTU-GV College of Engineering, Vizianagaram
Early diagnosis of neurodegenerative diseases is important for effective disease management and treatment planning. This paper presents a software–hardware co-design framework for six-class MRI-based classification of ALS, three Alzheimer’s Disease stages, Normal, and Others. During software training, pre-processed MRI images are used with pre-trained EfficientNetB0 for feature extraction, while SMOTE is applied only to the extracted training features to address class imbalance. A lightweight Custom CNN classifier is then trained using the balanced feature vectors. After training, the CNN weights and biases are converted to fixed-point representation and stored in hardware-compatible memory files. The trained classifier is implemented using Verilog HDL, synthesized in AMD Vivado, and integrated as a custom IP core on the PYNQ-Z2 FPGA. AXI-Stream and AXI DMA provide communication between the Processing System and Programmable Logic for hardware inference. The proposed framework demonstrates the feasibility of combining EfficientNetB0 feature extraction, SMOTE-based training, lightweight CNN classification, and FPGA acceleration to provide a resource-efficient and scalable solution for embedded MRI-based neurodegenerative disease classification.
KEYWORDS
This work presented a hardware–software co-design framework for six-class MRI classification of ALS, Alzheimer’s Stage 1, Alzheimer’s Stage 2, Alzheimer’s Stage 3, Normal, and Others. EfficientNetB0 was used during the software stage for feature extraction, while SMOTE was applied only to the training data to address class imbalance. A lightweight Custom CNN classifier was subsequently trained and its learned parameters were prepared for fixed-point hardware implementation. The trained classifier achieved an overall test accuracy of 96.79%, with a macro-average F1-score of 96.33%. The CNN accelerator was implemented using Verilog HDL and synthesized for the PYNQ-Z2-compatible Zynq-7020 device. The post-synthesis results showed 0.58% LUT, 0.03% flip-flop, 0.71% BRAM, and 30.45% DSP utilization, demonstrating the low hardware resource requirement of the proposed lightweight architecture. The proposed framework therefore demonstrates the feasibility of combining deep-learning-based MRI classification with FPGA acceleration. By separating software model development from hardware inference, the architecture provides a practical foundation for resource-efficient embedded AI applications. Future work will focus on improving the proposed system through larger and more diverse MRI datasets, additional independent validation, and further optimization of the lightweight Custom CNN architecture. The FPGA implementation can also be extended through post-implementation timing analysis, measured inference latency, power and energy evaluation, and further fixed-point optimization. Additional hardware parallelism and optimized memory/data-transfer architectures can be investigated to improve throughput. Finally, integration with more comprehensive clinical datasets and explainable AI techniques can be explored to improve the reliability and practical applicability of the proposed FPGA-based medical classification system.
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Publication Date
8/27/2026
Peer Review Type
Double-Blind Peer Review
Review Rounds: 2
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