Implementation and Evaluation of SIMD Instructions using RISC-V

Implementation and Evaluation of SIMD Instructions using RISC-V

Prof.Jaswanth V1,  Jeevan Kumar T M2, K V Sanjay3 , Manjunath B M4,

1Department of Electronics and Communication Engineering, Vidyavardhaka College of Engineering, jaswanthv@gmail.com

2Department of Electronics and Communication Engineering, Vidyavardhaka College of Engineering, g1kumartm@gmail.com

3Department of Electronics and Communication Engineering, Vidyavardhaka College of Engineering, sanjaykv1711@gmail.com

4Department of Electronics and Communication Engineering, Vidyavardhaka College of Engineering, manjunahthbm@gmail.com

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Abstract - This thesis introduces and explores the design and verification of a packed Single Instruction, Multiple Data (SIMD) instruction set for a RISC-V processor, known as the RISC-V P extension. This extension enhances the RISC-V instruction set architecture by providing packed SIMD support for 8-bit, 16-bit, and 32-bit integer data types. The significance of this architecture lies in its potential to empower developers in constructing more efficient and powerful data-parallel programs for RISC-V processors. This contribution enhances the overall capabilities of the RISC-V ecosystem, providing a valuable extension to the instruction set architecture for data-parallel applications.

Keywords: Data-parallel Programs, instruction set architecture,   RISC-V,   P extension, Packed SIMD