Implementation MAC Unit using Vedic Multiplier and Reversible Gates

Implementation MAC Unit using Vedic Multiplier and Reversible Gates

¹ Dr. Ch. Rajasekhara Rao, ²Sai Kishan Kranthi Kumar Vuriti, ³ Sasanam Renuka,⁴ Ichina Isha,⁵Bodda Dheeraj

,⁶ Bendi Gowthami

¹ Professor, ²³⁴⁵Students,

Department of Electronics and Communication Engineering

¹²³⁴⁵Aditya Institute of Technology and Management (A)-Tekkali, Andhra Pradesh.

Abstract: The design of Multiplier-Accumulator (MAC) unit can be implemented by using the Vedic multiplier and the reversible logic gates. The designing of Vedicmultiplier is designed by using four multiplier blocks and carry save adder. Theperformance of the MAC operation depends on the multiplier unit and the adder units. Here the designing of an adder can be implemented by using the reversible gates. In this project we use DKG reversible gate to increase the life time of the design. It can acts as full adder and full subtractor. Nowadays reversible gates are mostly used because it acts as heat controllers by this we can easily increase the life time of design. Here, we proposed 64-bit MAC using Vedic multiplier and the DKG adder. For better understanding we comparethis proposed 64bit MAC is with the basic MAC. Finally, it has been proved that the proposed MAC 10ns(time delay)isspeeder than basic MAC. The overall Simulation is carried out with Xilinx ISE 14.7.