Implementation of a Reconfigurable RV32I RISC-V with Five-Stage Pipelining Technique

RISC-V has found increased application in embedded systems and research work due to the growing demand for open, flexible, and low-cost CPU architectures. In an effort to improve hardware utilization and improve processor performance, this paper demonstrates the development and realization of the RV32I RISC-V core on FPGA. The processor employs a five-stage pipeline that consists of the required stages for a pipelined processor: Instruction Fetch, Instruction Decode, Execute, Memory Access, and Write Back stages. Supports the RV32I instruction set architecture. It also incorporates a custom- made hazard control unit that uses pipeline stalling and data forwarding to handle data and control hazards. It is implemented on a Zynq 7000 FPGA and modeled in Verilog HDL. Simulation was used to test the processor. To examine the functionality of the processor, execution of instructions, arithmetic and loop-oriented programs were used. This processor is suitable for real-world FPGA- based applications and processor development, since the pipelined architecture improves instruction throughput compared to non-pipelined execution while maintaining low estimated on-chip power and moderate resource usage.