Implementation of Dual-Use Power Lines to Improve Testability in CMOS Receiver Systems

Implementation of Dual-Use Power Lines to Improve Testability in CMOS Receiver Systems

Dr. S.HARI KRISHNAN

Associate Professor-ECE

Vice principal

P.Ganesh, P.Krishna Sai, S.Jayanth

Students of ECE

Sanskrithi school of engineering

Puttaparthi-515134

Abstract

        Power Line Communication (PLC) integrates the power distribution network and data communication over the same infrastructure, enabling efficient transmission of data. In this system, the power pins and the power distribution networks of ICs are used for both power delivery and data communication.
To facilitate the necessary communication across various nodes in an integrated circuit (IC), receivers are installed at each node or testing point within the system.
However, a significant challenge arises as the existing PLC receivers consume excessive power, which impacts the overall system efficiency, especially in energy-sensitive applications. To address this issue, We introduces the design of a power-efficient CMOS-based PLC receiver, implemented using the Tanner Tool.