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ArticlePeer ReviewedOpen AccessPlagiarism Passed
Paper ID:IJSREM14479

IMPLEMENTATION OF HARDWARE EFFICIENT LIGHT WEIGHT ENCRYPTION METHOD USING ITERATIVE ARCHITECTURE

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-

Subject:

-

Paper ID:

IJSREM14479

Volume:

6 |

6 |

Jun 2022

Pages:

Publication Frequency:

Monthly (12 issues per year)

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Not assigned

License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.

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Authors

SKS

Santhosh Kumar S

SN

Sethuraman N

VV

Vishal V

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Abstract

This paper proposes to implement a hardware efficient light weight encryption algorithm based on Light Encryption Device (LED). The hardware efficiency of a Light Encryption Device (LED) is mainly determined by the implementation of the Mix Columns operation. In order to reduce the computations involved, the. An iterative architecture is used to implement the designed LED algorithm, so that the hardware elements can be reused for every round operation. Further Block RAMs (BRAMs) are utilized for reducing area utilization. The proposed work is done for the block size of 64 bits and the key size of 128 bits and is targeted to Spartan 3E.

KEYWORDS

BRAMs Data Security Light weight cryptography VLSI.

Cite This Article

Santhosh Kumar S, Sethuraman N, Vishal V, "IMPLEMENTATION OF HARDWARE EFFICIENT LIGHT WEIGHT ENCRYPTION METHOD USING ITERATIVE ARCHITECTURE," International Journal of Scientific Research in Engineering and Management, vol. 6, no. 6, Jun 2022.

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Publication Date

6/14/2022

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Double-Blind Peer Review

Review Rounds: 2

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The authors declare no conflict of interest related to this research work.

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