IMPLEMENTATION OF HARDWARE EFFICIENT LIGHT WEIGHT ENCRYPTION METHOD USING ITERATIVE ARCHITECTURE

IMPLEMENTATION OF HARDWARE EFFICIENT LIGHT WEIGHT ENCRYPTION METHOD USING ITERATIVE ARCHITECTURE

Santhosh Kumar S, Sethuraman N, Vishal V

Electronics and Communication Engineering, Velammal College of Engineering and Technology, Madurai.

Abstract— This paper proposes to implement a hardware efficient light weight encryption algorithm based on Light Encryption Device (LED). The hardware efficiency of a Light Encryption Device (LED) is mainly determined by the implementation of the Mix Columns operation. In order to reduce the computations involved, the. An iterative architecture is used to implement the designed LED algorithm, so that the hardware elements can be reused for every round operation. Further Block RAMs (BRAMs) are utilized for reducing area utilization. The proposed work is done for the block size of 64 bits and the key size of 128 bits and is targeted to Spartan 3E.

Index Terms—BRAMs, Data Security, Light weight cryptography, VLSI.