Implementation of High Data Rate Digital Transmission Low Power Current Starved Ring VCO Design

Implementation of High Data Rate Digital Transmission Low Power Current Starved Ring VCO Design

Reena Pal1 ,Dr.Shiksha Jain2 ,Er.Deepika Verma3

Department of Electronics and Communication Engineering, Institute of Engineering and Technology,

 Dr Ram Manohar Lohia Avadh University, Ayodhya, Uttar Pradesh, India zx.renupal16265@gmail.com

Abstract: This project aims to construct a radio frequency (1.8GHz) low power PLL using a 0.18-m CMOS technology. Current Starved VCO and Differential Pair VCO evaluations for low electricity and high frequency evaluations, respectively, have been carried out and analyzed. Spice has created and simulated every PLL component in the Tanner EDA in the 0.18-m era. After both designs were simulated in the same environment, two of the most crucial VLSI restrictions—speed (high frequency range) and power intake—were examined. The advantages of the current-starved-based VCO's decreased energy consumption have been compared to the differential VCO's quick speed and locking performance.

Keywords: Charge pump, Current Starved VCO, PLL, Phase noise, and VCO.