Implementation of the High Speed PLL

the most multipurpose application of the phase locked loops (PLL) is for clock generation and clockrecovery in microprocessor, networking, communication systems, and digital circuit and frequency synthesizers.Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks inhighperformance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter (deviation) reduction. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with fasterlocking ability. Many present communication systems operate in the GHz frequency range. Hence there is a necessity of a PLL which must operate in the GHz range with less lock time.PLL is a mixed signal circuit as itsarchitecture involves both digital and analog signalprocessing units. The present work focuses on the redesign of a PLL system using the 90 nm process technology (GPDK090 library) in EDA TANNER Design Environment.Here a current starved ring oscillator has been considered for its superior performance in form ofits low chip area, low power consumption and wide tunable frequency range. Thesimulation results ofPLL are reported in this work. It is found that the designed PLL consumes 11.68mW power froma 1.8V D.C. supply and have a lock time 280.6 ns. As the voltage controlled oscillator (VCO) isthe heart of the PLL, so the optimization of the VCO circuit is also carried out using the optimization technique. The results of the VCO designed are shown.