IMPLEMENTATION OF UART WITH STATUS REGISTER USING VHDL

Today in real world the actual applications, usually needed only a few key features of UART. Specific interface chip will cause waste of resources and increased cost. Particularly in the field of electronic design, SOC technology is recently becoming increasingly mature. This situation results in the requirement of realizing the whole system function in a single or a very few chips. Universal Asynchronous Receiver Transmitter (UART) is a kind of serial communication protocol. In parallel communication the cost as well as complexity of the system increases due to simultaneous transmission of data bits on multiple wires. Serial communication alleviates this drawback of parallel communication and emerges effectively in many applications for long distance communication as it reduces the signal distortion because of its simple structure. The UART implemented with VHDL language can be integrated into the FPGA to achieve compact, stable and reliable data transmission. Advanced Peripheral Bus (APB) is used for solved interfacing problem. With APB other devices are easy to connect with UART. The proposed design of UART satisfies the system requirements of high integration, stabilization, low bit error rate, and low cost. It also supports configurable baud rate generator and variable data length from 5-8 bits per frame. This project focuses on the VHDL implementation of UART with status register which supports asynchronous serial communication. The project presents the architecture of UART which indicates, during reception of data, parity error, framing error, overrun error and break error using status register. For solving interfacing complexity used an APB.