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ArticlePeer ReviewedOpen AccessPlagiarism Passed
Paper ID:10.55041/IJSREM29532

Instruction Level Parallelism and Memory Synchronization

Stream/Area:

-

Subject:

-

Paper ID:

10.55041/IJSREM29532

Volume:

8 |

3 |

Mar 2024

Pages:

Publication Frequency:

Monthly (12 issues per year)

DOI
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10.55041/IJSREM29532

License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.

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Rupam Sardar

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Abstract

The simultaneous or parallel execution of a series of instructions within a computer program is known as instruction-level parallelism, or ILP. ILP stands for the average number of instructions executed throughout each stage of this parallel execution, to be more precise. The architecture known as instruction level parallelism (ILP) allows for the execution of several operations in parallel within a single process, each with its own set of resources, including address space, registers, identifiers, state, and program counters. It describes compiler design strategies and processors intended to carry out operations in parallel to increase processor performance, such as memory load and store, integer addition, and float multiplication.

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Rupam Sardar, "Instruction Level Parallelism and Memory Synchronization," International Journal of Scientific Research in Engineering and Management, vol. 8, no. 3, Mar 2024. https://doi.org/10.55041/IJSREM29532

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