Localization of a Robot on FPGA with 5-Stage Pipeline RISC-V CPU

Localization of a Robot on FPGA with 5-Stage Pipeline RISC-V CPU

Dr. K S Geetha
RVCE, Bengaluru, India

Sai Surya Sreekar Mulukutla
RVCE, Bengaluru, India

Deepika M
RVCE, Bengaluru, India

Mrudhul M J
RVCE, Bengaluru, India

S Vedram
RVCE, Bengaluru, India

Abstract—Custom silicon offers an untapped opportunity for addressing complex challenges in robotics by providing optimized performance and energy efficiency. RISC-V—a novel, open- source Instruction Set Architecture (ISA)—has been gaining rapid traction due to its flexibility and customizability. In this work, we explore the capabilities of RISC-V in the robotics do- main by implementing a complete localization and motion control solution on an FPGA. Leveraging the reconfigurability of FPGAs alongside the extensibility of a custom five-stage pipelined RISC- V processor, our approach demonstrates significant potential for real-time, efficient, and scalable robotic applications. Extensive testing reveals that hardware-level acceleration, particularly in sensor fusion and motor control, provides substantial improve- ments in latency and computational efficiency over traditional software-based systems. The results underscore the promise of RISC-V-based hardware acceleration for advanced robotic localization and pave the way for future innovations in embedded robotics.

Index Terms—FPGA, RISC-V, Localization, Robotics, Custom Silicon, Instruction Set Architecture, Real-time Processing, Hard- ware Acceleration