Low-Power Implementation of Sobel Edge Detection Algorithm Using Verilog HDL

Edge detection is a fundamental operation inimage processing, widely used in applications such as object recognition, medical imaging, pattern recognition, and computer vision. It identifies significant intensity changes in an image that correspond to object boundaries and structural details. Among various techniques, the Sobel operator is commonly used due to its simplicity and efficiency in approximating image gradients using horizontal and vertical convolution masks. However, the conventional Sobel method has limitations, including sensitivity to noise, restricted directional detection, and reduced accuracy in capturing fine or diagonal edges. To address these issues, this project proposes a low- power Sobel Edge-8 detection algorithm implemented using Verilog. The enhanced approach computes gradients in eight different directions, enabling better detection of edges with varying orientations and finer details. The system is designed using Verilog HDL and evaluated through simulation and synthesisusingXilinxVivadoandMATLABR2020a.Results show improved edge detection accuracy with low computational complexity, making the design suitable forreal-time image processing and embedded vision applications due to its high speed, efficiency, reliability, and low power consumption.