Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer

Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer

Rahul Singh Paikra*, Dr.Devanand Bhonsle **

*-**Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Technical Campus, Bhilai, Durg, Chhattisgarh, India.

Abstract

In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processors. To address this issue, a novel single phase-clock dual-edge-triggering (DET) FF using a single-transistor clocked (STC) buffer (STCB) is proposed. The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transitions (RTs) and internal RTs that exist in other DET designs. Verified by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, when operating at switching activity, the proposed STC-DET outperforms prior state-of-the-art low power DET in power consumption It also achieves the lowest power-delay-product (PDP) among the DETs.

Keywords: Dual edge triggering (DET), dynamic power, flip-flop.