Low-Power Transmission Gate-Based SRAM Architecture with Dynamic Power Gating for Sub-Threshold Applications

The growing demand for energy-efficient memory in sub-threshold computing environments, especially in IoT and embedded systems, necessitates the development of optimized SRAM architectures. Traditional 6T and 8T SRAM cells suffer from high leakage power, increased latency, and poor scalability. This work presents two novel design methodologies to address these limitations. The first incorporates Transmission Gate (TG) logic to improve read access stability and reduce delay. The second integrates a dynamic power gating scheme to minimize leakage power and enhance overall energy efficiency. The proposed designs are modeled and evaluated using the Tanner EDA tool with 45nm technology files. Simulation results demonstrate over 80% reduction in latency and significant power savings compared to conventional SRAM designs, highlighting the architecture’s suitability for low-power, high-performance applications in modern SoC and IoT systems.