Low-Power VLSI Design in Full Adder Using Body-Biasing Techniques

This paper presents five distinct low-power full adder designs based on XOR/XNOR gates and multiplexer blocks, enhanced through body biasing techniques. In the first approach, the adder achieves a power dissipation of 204.09 µW with a delay of 5.9849 ns. The second method shows improved power efficiency, reducing consumption to 128.92 µW and exhibiting a delay of 5.9875 ns, thanks to the use of voltage biasing on two PMOS transistors (P1 and P2) alongside substrate biasing. The third design significantly minimizes power dissipation to 0.223 nW, with a delay of 5.2352 ns. An even lower power consumption of 0.199 nW is observed in the fourth methodology, which operates with a delay of 5.1002 ns. Finally, the fifth design further reduces minimum power to 0.192 nW. Additionally, the power delay product (PDP) has been analyzed across all proposed methods. When compared to previously reported designs, the proposed adders demonstrate superior performance in both power efficiency and delay.