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Stream/Area:
-
Subject:
-
Paper ID:
IJSREM67970
Volume:
10 |
10 |
Oct 2026
Pages:
1-3
Publication Frequency:
Monthly (12 issues per year)
License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.
Electronics and Communication Engineering
CMR Technical Campus
Electronics and Communication Engineering
CMR Technical Campus
Electronics and Communication Engineering
CMR Technical Campus
Electronics and Communication Engineering
CMR Technical Campus
Electronics and Communication Engineering
CMR Technical Campus
Electronics and Communication Engineering
CMR Technical Campus
Efficient arithmetic hardware is essential for modern computing systems, especially in artificial intelligence and digital signal processing. This paper presents the design and functional simulation of a 2×2 Multiply–Accumulate (MAC) array developed using Verilog HDL. The architecture is organized to execute multiplication and accumulation operations in parallel, improving processing efficiency while maintaining a simple and modular structure. The proposed design is verified through simulation in Xilinx Vivado 2016.2 using a dedicated testbench. The obtained results demonstrate correct functionality for the applied input values and validate the reliability of the design. The developed MAC array serves as a basic building block that can be expanded for larger hardware accelerators and FPGA-based applications in the future.
KEYWORDS
Overall, the design has been successfully verified at the simulation level and demonstrates reliable performance. The MAC unit array shows parallel processing capability, which is very important in applications such as digital signal processing, image processing, matrix multiplication, and AI hardware accelerators. In future work, the design can be implemented on FPGA hardware and further optimized to improve speed, reduce hardware area, and minimize power consumption. This would make the MAC unit array more efficient and suitable for real-time AI accelerator applications.
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Publication Date
10/14/2026
Peer Review Type
Double-Blind Peer Review
Review Rounds: 2
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Conflict of Interest
The authors declare no conflict of interest related to this research work.
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