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Paper ID:IJSREM67970

MAC Unit Design For AI Accelerator

Stream/Area:

-

Subject:

-

Paper ID:

IJSREM67970

Volume:

10 |

10 |

Oct 2026

Pages:

1-3

Publication Frequency:

Monthly (12 issues per year)

DOI
Digital Object Identifier
10.55041/IJSREM67970

License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.

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Authors

SM

Sudhamalla Mallesh

Electronics and Communication Engineering

CMR Technical Campus

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UM

Umeshchandra Mansuju

Electronics and Communication Engineering

CMR Technical Campus

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SY

Shivani Yelgapuri

Electronics and Communication Engineering

CMR Technical Campus

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LN

Laxmikanth Nareddy

Electronics and Communication Engineering

CMR Technical Campus

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SD

Srinivas Desireddy

Electronics and Communication Engineering

CMR Technical Campus

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Mentors

SM

Sudhamalla Mallesh

Electronics and Communication Engineering

CMR Technical Campus

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Abstract

Efficient arithmetic hardware is essential for modern computing systems, especially in artificial intelligence and digital signal processing. This paper presents the design and functional simulation of a 2×2 Multiply–Accumulate (MAC) array developed using Verilog HDL. The architecture is organized to execute multiplication and accumulation operations in parallel, improving processing efficiency while maintaining a simple and modular structure. The proposed design is verified through simulation in Xilinx Vivado 2016.2 using a dedicated testbench. The obtained results demonstrate correct functionality for the applied input values and validate the reliability of the design. The developed MAC array serves as a basic building block that can be expanded for larger hardware accelerators and FPGA-based applications in the future.

KEYWORDS

Multiply–Accumulate (MAC) Verilog HDL Vivado Digital Design FPGA Parallel Processing.

Cite This Article

Sudhamalla Mallesh, Umeshchandra Mansuju, Shivani Yelgapuri, Laxmikanth Nareddy, Srinivas Desireddy, Sudhamalla Mallesh, "MAC Unit Design For AI Accelerator," International Journal of Scientific Research in Engineering and Management, vol. 10, no. 10, pp. 1-3, Oct 2026. https://doi.org/10.55041/IJSREM67970

Full Article/Conclusion

Overall, the design has been successfully verified at the simulation level and demonstrates reliable performance. The MAC unit array shows parallel processing capability, which is very important in applications such as digital signal processing, image processing, matrix multiplication, and AI hardware accelerators. In future work, the design can be implemented on FPGA hardware and further optimized to improve speed, reduce hardware area, and minimize power consumption. This would make the MAC unit array more efficient and suitable for real-time AI accelerator applications.

References

[1]     Umadevi, S., Penumaka, P., Ram, C. K. & Devi, T. K. High performance MAC unit design with grouping and decompositionmultiplier and 18 T gate diffusion Input-Transmission gate adder. Circuits Syst. Signal. Process. 44 (4), 2830–2854 (2025). [2]     Niknia, F. et al. A Configurable Floating-Point Fused Multiply-Add Design with Mixed Precision for AI Accelerators. IEEETransactions on Circuits and Systems for Artificial Intelligence. (2025). [3]     Dabbagh, A., Karamimanesh, M., Hassanli, K. & Abiri, E. CD-MAC: mixed signal binary/ternary in-memory computingaccelerator for power-constrained MAC processing. J. Supercomputing. 81 (1), 190 (2025). [4]     R. Sun, Y. Ni, X. He, J. Zhao, and A. Zou, ONE-SA: Enabling nonlinear operations in systolic arrays for efficient and flexibleneural network inference, in Proc. 2024 Design, Automation & Test in Europe Conf. & Exhibition, Valencia, Spain, 2024, pp. 1–6. [5]     K. Anderson, Hardware for machine learning inference: CPUs, GPUs, TPUs, https://telnyx.com/resources/ hardware-for-machine-learning-inference-cpus gpus-tpus, 2023. [6]     M.Jiang,J.Wang,A.Eldebiky,X.Yin,C.Zhuo,I.C.Lin,andG.L.Zhang,“aware pruning for efficient neural networks, ”in Design,Automation and Testin Europe(DATE),2024. [7]     J.Wang, B.Li, and G.L.Zhang, “Early exit with class exclusion for efficient in reference of neural networks,” in InternationalConference on Artificial Intelligence Circuits and Systems (AICAS),2024. [8]     Kashif Inayat, Fahad Bin Muslim, Javed Iqbal, Syed Agha Hassnain Mohsan, Hend Khalid Alkahtani and Samih M. Mostafa:“Power-Intent Systolic Array Using Modified Parallel Multiplier for Machine Learning Acceleration. Sensors”2023. [9]     Inayat, K.; Chung, J. “Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration”. IEEE Trans. VeryLarge-Scale Integration. (VLSI) Syst. 2022. [10]   Jeyakumar Ponraj, R. Jeya bharath, P. Veena, Tharumar Srihari, “High performance multiply accumulate unit by integratingbinary carry select adder and counter-based modular wall ace tree multiplier for embedding system”, the VLSI Journal 23(2023).

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Publication Date

10/14/2026

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Review Rounds: 2

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