Modified High Speed 32 Bit Vedic Multiplier Design and Implementation

Multipliers are essential components in digital signal processing, image processing, and communication systems where high-speed arithmetic operations are required. Conventional multipliers suffer from increased propagation delay and hardware complexity as operand size increases. This paper presents a modified 32-bit Vedic multiplier based on the Urdhva-Tiryakbhyam algorithm of Vedic mathematics. The proposed architecture divides operands into smaller sub-blocks to enable parallel generation of partial products, thereby reducing computation delay. An optimized adder structure is used to combine intermediate results efficiently. The design is implemented using Verilog HDL and simulated using Xilinx tools. Simulation results demonstrate improved speed, reduced delay, and efficient hardware utilization suitable for high-performance VLSI applications.