Optimized AES algorithm for Trojan Detection via Area Reduction

Optimized AES algorithm for Trojan Detection via Area Reduction

Shaik Mahammad Maaz
dept. of ECE

Institute of Aeronautical Engineering Hyderabad, India 18maazshaik@gmail.com

Ms. C.Radhika, Assistant professor
dept. of ECE

Institute of Aeronautical Engineering Hyderabad, India c.radhika@iare.ac.in

G. Vijay Kumar

dept. of ECE

Institute of Aeronautical Engineering Hyderabad, India rgaddikopula@gmail.com

T.Komalasai

dept. of ECE

Institute of Aeronautical Engineering Hyderabad, India komalasai2323@gmail.com

Abstract—The integration of the Advanced Encryption Stan- dard (AES) into hardware platforms introduces significant se- curity challenges, particularly concerning the potential insertion of hardware Trojans designed to compromise system security without detection. These Trojans, often employing area reduction tactics to minimize their physical footprint, evade conventional detection methods that rely on anomalies in chip area utilization or power consumption. To counteract these stealthy threats, a multifaceted approach is essential. Functional verification ensures correct AES implementation by rigorous testing against reference models, while side-channel analysis detects unintended informa- tion leakage through power, electromagnetic, or timing variations. Layout inspection examines the physical chip for irregularities using advanced imaging techniques, and behavioral analysis monitors runtime execution patterns to identify performance anomalies. Formal verification employs mathematical proofs to validate the design against security properties. Combining these methodologies enhances the detection and mitigation of area- reduction Trojans, bolstering the trustworthiness and resilience of AES-based cryptographic systems.

Index Terms—Optimized AES,Trojan Detection,Hardware Trojan,Area Reduction,AES Algorithm Optimization, VLSI De- sign,FPGA Implementation, AES Encryption