Optimized FIR Filter Architecture Using Vedic Multiplier and Carry Lookahead Adder

The increasing demand for high-performance and low-power digital signal processing (DSP) systems requires efficient arithmetic architectures, particularly in Finite Impulse Response (FIR) filters where multipliers and adders dominate the hardware cost. The existing FIR design utilizes Weinberger adders, composite adders, and Weinberger-based multipliers to achieve improved performance; however, the complex carry-generation structure and multi-stage adder trees lead to higher LUT usage and increased dynamic power. To overcome these limitations, this work proposes an optimized FIR architecture that integrates a Vedic (Urdhva–Tiryagbhyam) 8×8 multiplier and a high-speed Carry Lookahead Adder (CLA). The Vedic multiplier provides fast parallel partial-product generation with reduced logic depth, while the CLA significantly shortens carry propagation delay. The proposed design reduces the number of LUTs, decreases switching activity, and achieves lower dynamic power compared to the existing Weinberger-based structure. Simulation and synthesis results in Vivado confirm that the proposed architecture enhances speed, lowers power consumption, and offers an area-efficient solution suitable for modern low-power DSP applications.