Out-of-Order Superscalar Execution: Resolving Data Hazards in MIPS Architecture

Out-of-Order Superscalar Execution: Resolving Data Hazards in MIPS Architecture

Subrahmanya Rao D P
Dept. of ECE

RV College of Engineering Bangaluru, India Subrahmanyardp.ec21@rvce.edu.in

Charan H A
Dept. of ECE

RV College of Engineering Bangaluru, India charanha.ec21@rvce.edu.in

Shravankumar N Biradar
Dept. of ECE

RV College of Engineering Bangaluru, India shravankumarnb.ec21@rvce.edu.in

Dr. Jayanthi P N
Dept. of ECE

RV College of Engineering Bangaluru, India jayanthipn@rvce.edu.in

Aishwarya H
Dept. of ECE

RV College of Engineering Bangaluru, India aishwaryah.ec21@rvce.edu.in

Abstract—Out-of-order superscalar execution is a critical advancement in modern processor architectures, enhancing instruction-level parallelism (ILP) and mitigating performance bottlenecks. This paper explores the implementation of super- scalar execution in MIPS architecture, focusing on resolving data hazards such as Read-After-Write (RAW), Write-After- Read (WAR), and Write-After-Write (WAW). Techniques like Tomasulo’s algorithm, register renaming, reservation stations, and branch prediction are employed to optimize execution flow. A Python-based simulation demonstrates improved throughput, reduced stalls, and efficient CPU resource utilization. The results highlight the impact of dynamic scheduling and speculative execution in maximizing computational efficiency, contributing to the evolution of high-performance processor designs